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Decoding the Memory Landscape: Intel’s Integration Play, NAND Supply Crunches, and the 2028 Horizon

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August 19, 2026

The memory market’s booming transformation is driven by the growing demand for Cloud AI infrastructure. While mainstream headlines focus on high-bandwidth memory (HBM) supply allocations, the underlying dynamics across manufacturing CAPEX, enterprise storage, and system architectures tell a more nuanced story. 

1. Intel's Memory Play: Integration Over Manufacturing

Recent high-profile executive hires have sparked speculation about Intel re-entering the memory market. However, a return to direct DRAM or NAND wafer fabrication is financially and operationally improbable in the near- to mid-term: 

CAPEX Constraints:

Greenfield memory fabs demand billions in ongoing capital expenditure with notoriously cyclical margins. These also take 3-4 years to build.

Process IP Gap:

  • Intel was originally a memory pioneer (founding its early business on SRAM and DRAM) before exiting standard DRAM manufacturing in the mid-1980s under Andy Grove due to intense competition from Japanese manufacturers.  
  • Intel retained its proprietary non-volatile Optane memory during the initial SK Hynix deal but officially wound down the Optane business in 2022 due to high development costs and low industry adoption. The deal was executed in a two-stage transaction: 
  • Phase 1 (December 2021): SK Hynix paid $7 billion to acquire Intel’s NAND SSD business (rebranded under SK Hynix as Solidigm), associated SSD IP, and the 12-inch wafer manufacturing facility in Dalian, China. 
  • Phase 2 (March 2025): SK Hynix paid the remaining ~$1.9–$2 billion to acquire the remaining NAND wafer design IP, R&D workforce, and manufacturing employees, completing Intel's full exit from NAND production. 


Integration where the Value is:

Instead, Intel’s memory presence will be realized through packaging and architectural interfaces. By pairing its CPU portfolio with EMIB advanced packaging, chiplet interconnects, and leadership in CXL (Compute Express Link), Intel can capture value at the memory-compute junction without bearing the burden of commodity wafer manufacturing. 

Read more: The $Trillion Bottleneck: Intel Bets EMIB, ZAM and XBM Against TSMC’s CoWoS

2. Fab Dynamics: Maintenance vs. Expansion

Recent capacity announcements require careful interpretation regarding net-new output versus process-yield preservation.

Initiative / PlayerStated MoveMarket Reality
SK Hynix (Dalian, China)~50k wafers/monthDefensive Maintenance: Represents 3–4% of global capacity; primarily offsets throughput loss from rising node complexity. Supplementary Fab.
YMTC (China)Fabs 1–3 operational. Long-Term Fab 10Long-term Scaling: Multi-fab roadmap remains uninterrupted by foreign legacy fab adjustments.
Big 3 (Samsung, SK Hynix, Micron)2H 2027 output plans2028 Relief: Fab construction timelines mean commercial volume ramps will not balance supply until 2028.

3. The Unsung Driver: Why NAND Is Outpacing DRAM

Although DRAM captures attention via HBM allocation, NAND spot and contract prices have shown sharper upward pressure.

  • The AI Inference Storage Bottleneck: The scaling of large language models requires massive, low-latency storage for KV (Key-Value) cache states. 
  • eSSD Cannibalization: To satisfy enterprise AI infrastructure, memory makers are prioritizing high-capacity enterprise SSDs (eSSDs). This shift drains wafer allocation away from standard consumer NAND, tightening broad-market supply.
  • Emerging Formats on Hold: Next-generation architectures such as High-Bandwidth Flash (HBF) remain in development phases without binding customer volume commitments, pushing material relief to 2028. 

Read more: How SanDisk is planning NAND innovations and a business model to cater to ongoing demand 

Strategic Outlook

The memory cycle is shifting from pure bit-growth volume to architecture-specific allocation. Relief from current supply constraints remains tethered to long fab ramp horizons, keeping pricing firm through mid-decade, through 2028 at least, while shifting competitive differentiation toward packaging (EMIB, XBM, CoWoS R, etc) and system-level interconnects (CXL, Disaggregated Memory, etc).

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Author

Neil Shah

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Neil is a sought-after frequently-quoted Industry Analyst with a wide spectrum of rich multifunctional experience. He is a knowledgeable, adept, and accomplished strategist. In the last 18 years he has offered expert strategic advice that has been highly regarded across different industries especially in telecom. Prior to Counterpoint, Neil worked at Strategy Analytics as a Senior Analyst (Telecom). Neil also had an opportunity to work with Philips Electronics in multiple roles. He is also an IEEE Certified Wireless Professional with a Master of Science (Telecommunications & Business) from the University of Maryland, College Park, USA.