Memory Solutions for Gen AI Part 6: Edge Computing

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Mar 3, 2025

Semiconductor innovation is at the center of the technology that improves our lives. In this space, companies are pursuing a flexible approach to secure better return on invested capital (ROIC). In addition, cooperation with the supply chain has become more necessary than ever in the chiplet architecture. We are also seeing changes in hardware, adapting to changes in Gen AI use and the user interface.

Who’s driving what in 2025-2027?

No Solution is Perfect: DRAM solutions have their own advantages and disadvantages. These technologies improve characteristics like bandwidth, latency, speed, capacity, and power consumption/heat. However, they also come with costs and timeliness challenges. To mitigate the risks associated with innovation, customers need to make commitments, while manufacturers need to reduce cost burdens.

Smartphone and Apple: In the short term, the most innovative solution is Processing-In-Memory (PIM), but in limited quantities to support Neural Processing Units (NPU). Mobile High Bandwidth Memory (HBM) could enhance performance, but applications are still unclear. In 2026, Apple is expected to shift from Package-on-Package (PoP) to discrete in the iPhone Pro Max and foldable phones, thereby increasing bandwidth.
NAND performance is also expected to improve through UFS 5.0.

Auto and Tesla: As autonomous driving expands, the use of faster Application Processors (AP) and Low Power Double Data Rate (LPDDR) memory is increasing. The utilization of HBM4 in autonomous vehicles is expected to start after 2027. In the case of Extended Reality (XR), drones, and gaming, the use of Wide I/O is anticipated to expand to improve latency. However, product roadmaps remain unclear.

NVIDIA and SOCAMM: NVIDIA's proposed DIGITS technology aims to expand memory bandwidth through the combination of GPUs and HBM, as well as enhance CPU bandwidth through SOCAMM around mid-year 2025, allowing for greater capacity expansion and improved signal integrity compared to on board LPDDR. However, with the cost burden of PCB and connectors, there are currently no plans to apply this to general PCs.

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Summary

Published

Mar 3, 2025

Author

MS Hwang

MS Hwang is a research director at Counterpoint, specializing in memory semiconductor research. MS Hwang brings over 30 years of experience from Samsung Electronics and sell-side brokerage research roles including ABN AMRO, Goldman Sachs, Credit Suisse and Samsung Securities.