- d-Matrix inverted the stack: Logic on top, custom DRAM underneath acting as the interposer. That single choice sidesteps most of the thermal ceiling imec identified for 3D HBM-on-GPU, and it is why the capacity is only 32GB.
- 36-micron face-to-face is deliberately unaggressive: It is microbump, not hybrid bonding, which preserves known-good-die sorting and the economics that wafer-to-wafer bonding in the Qualcomm HBC could struggle with.
- The number that matters is 0.37 pJ/bit, measured on early silicon, against roughly 2.4 pJ/bit to move a bit into an HBM4 base die. It is real because the PHY is gone, not because the DRAM is better.
- Against its own predecessor, Raptor is a capacity product, not a bandwidth one: Sixteen times Corsair's fast-tier capacity at roughly two-thirds its bandwidth. Comparing it with HBM misses the point.
- Nobody has said who fabricates the DRAM die: SK hynix has been a shareholder since 2022 and Samsung Ventures since 2023, but there is still no public commitment from a custom DRAM supplier.
- Alchip winning the socket is a packaging win, not a co-design win and worth less in dollars than in signal. Broadcom and Marvell still hold the co-design market, with MediaTek making inroads.
- If DRAM-on-logic reaches volume, the custom HBM base die is an interim step: But only in decode-bound inference. Capacity, not bandwidth, is what keeps HBM in training.
Decoding D-Matrix’s Recent Announcements
At ISCA 2026 in June, d-Matrix and the University of British Columbia published a very interesting paper on early silicon of Raptor, described as the first 3D-DRAM accelerator for generative inference. It reports measurements from a working vertical interface, and projects roughly 4.7× higher inference throughput per accelerator than an HBM-based configuration and about 2.4× against an SRAM-based one.
At Hot Chips 2026 in August, co-founder and CTO Sudeep Bhoja presented the architecture with Aayush Ankit, who led Raptor's SoC architecture before moving to Meta's MTIA team. The key architectural point is a TSMC N4 logic die bonded face-to-face at a 36-micron pitch onto a custom-designed DRAM die, delivering more than 100 TB/s from 32GB per accelerator at 0.37 pJ/bit.
On 10 September 2026, d-Matrix announced it had joined NVIDIA's NVLink Fusion ecosystem, putting Raptor XPUs into MGX racks alongside Vera CPUs, NVLink switches, BlueField-4 DPUs and Spectrum-X networking, with Astera Labs supplying connectivity. Raptor is expected to tape out before the end of 2026; rack availability is stated as Q4 2027.
Raptor succeeds Corsair, d-Matrix's shipping digital in-memory compute platform. This evolves back to Pavehawk, the 3DIMC test vehicle validated in d-Matrix's labs and announced with Alchip in November 2025. Pavehawk is why d-Matrix can use the word measured at all: it showed that a face-to-face bonded logic-on-DRAM stack can be assembled, powered and characterised electrically. It says nothing about yield at volume, thermals under sustained load or system throughput, and d-Matrix itself named four open problems: bank-to-channel mapping, I/O power, thermal reliability and yield.
The Architectural move is Replacing rather than Redesigning
Every approach covered in this $Trillion series so far has been around redesigning the logic-memory boundary. Marvell and NVIDIA replace the JEDEC bus with a private serialised link. Intel's XBM and ZAM restructure the stack. Qualcomm's HBC puts compute beneath the DRAM. All of them still move data between two dies, and all of them keep separate thermal domains.
FIGURE 1. Source: Counterpoint Research. D-Matrix
Read the full report: The $Trillion Bottleneck: d-Matrix Raptor, AlChip and the Case Against Custom HBM
Similar blogs from the series:
The $Trillion Bottleneck: Memory Wall :: Intel Bets EMIB, ZAM and XBM Against TSMC’s CoWoS
The $Trillion Bottleneck: Memory Wall :: Inside Qualcomm's High Bandwidth Compute (HBC) Bet
The $Trillion Bottleneck: Memory Wall :: NVIDIA's NVHBM and the Fight for the Base Die
