As AI compute gets faster, memory bandwidth is emerging as a critical bottleneck, creating what the industry calls the “memory wall.” At the Snapdragon Summit 2026 in Maui, Ritesh Bendre sat down with Qualcomm’s Durga Malladi to discuss how High Bandwidth Compute (HBC) aims to address the memory wall challenge by bringing compute closer to memory.
Durga also explains how HBC could extend beyond data centres to PCs, smartphones, automotive and XR devices. This is particularly important in the agentic AI era, where devices need to process AI workloads continuously without significantly impacting battery life.
The Interview
Key Takeaways from the Discussion
Understanding the Memory Wall
• Traditionally, computing architectures separate the processor from memory, which requires data to move back and forth between the two.
• Over the years, compute capabilities have advanced rapidly, but memory bandwidth has struggled to keep pace, leaving processors waiting for data.
• This growing disparity creates the “memory wall”, a bottleneck that limits overall computing performance despite processors getting increasingly powerful.
How Qualcomm’s High Bandwidth Compute (HBC) Works
• Qualcomm’s unique approach with HBC focuses on bringing compute closer to memory.
• This solution enables low latency between compute and memory, thus reducing the time needed to access data.
• The approach also helps reduce data movement, which in turn lowers power consumption, a critical consideration for demanding AI workloads.
• By addressing the memory bottleneck, HBC also aims to improve overall computing efficiency and performance per watt.
Beyond Data Centres: Enabling Agentic AI Across Devices
• As we move into the agentic AI era, AI agents will require efficient computing without significantly increasing power consumption to continuously process requests and anticipate tasks.
• Malladi noted that beyond data centres, the HBC approach can also be extended to automotive systems, extended reality (XR) devices, PCs and smartphones.
Analyst Take
• HBC is not simply a variant of custom HBM; it’s all about minimising data movement from memory to the accelerator.
• Architecturally, it places a compute die beneath a 3D-stacked LPDDR array on a standard organic substrate, a direct challenge to the HBM-plus-interposer packaging that underpins today’s AI accelerators.
• The commercial case, however, remains unproven: Gen 1 is not expected to sample until mid-2027 and Gen 2 until 2028, and no independent benchmarks are available yet.
• That runway gives competitors time to catch up. Ultimately, software and toolchain maturity will be key.
