Overview

At its 2026 North America OIP Ecosystem Forum in Santa Clara, TSMC argued that process, package, optics and the design flow now ship as one product. This is the fifth report in the Trillion-Dollar Bottleneck series. It decodes what TSMC actually announced, from the AI Design Kit (ADK) to a packaging roadmap running to 2029 and 3D DRAM appearing on that roadmap. It also assesses what the bundling strategy means for TSMC's lead in the angstrom era.

What the Full Report Will Cover

  • TSMC AI Design Kit (ADK): how agents trained on TSMC's design history replace the human-facing PDK, the task-level speed-ups claimed, and the open questions on data ownership, process IP and pricing
  • A14 tool readiness: EDA certification from Cadence, Siemens and Synopsys, and why certifying tools is not the same as certifying agents
  • CoWoS and SoIC roadmap to 2029: package scaling, HBM stack counts, and the thermal and power signoff gaps
  • 3D DRAM and HBM timelines: what DRAM-on-logic means for HBM5/HBM5E and the custom base-die efforts
  • TSMC COUPE vs GlobalFoundries SCALE: two different approaches to co-packaged optics compared
  • Demand drivers and competition: Broadcom's view on growing package sizes, Intel EMIB-T and Samsung's alternatives, and memory supply as TSMC's dependency
  • Claim-by-claim check: which figures from the event are verifiable and which conflict across sessions
  • Three scenarios: how the bundle could hold, fragment, or be capped by memory supply

 

Who Should Read This

  • Semiconductor and foundry executives and strategy teams
  • Fabless, ASIC and hyperscaler teams planning AI accelerator programs
  • EDA, IP and advanced packaging ecosystem players
  • Memory makers (DRAM/HBM) and optical/silicon photonics companies
  • Investors and analysts tracking TSMC, its competitors and the AI supply chain

 

Key Questions the Report Answers

  • What did TSMC actually announce at OIP 2026, and what is only roadmap?
  • How does the ADK change chip design, and who owns the data and IP behind it?
  • Are EDA tools ready for A14, and how can agent-made design changes be certified?
  • How far can CoWoS scale by 2029, and what limits it?
  • Does 3D DRAM on logic threaten custom HBM base-die projects?
  • How do TSMC COUPE and GF SCALE differ, and do they compete?
  • Can Intel or Samsung win AI packaging business from TSMC?
  • Which numbers presented at the event should analysts treat with caution?