Overview

CXMT and Micron have taken sharply opposing positions on 4F² (vertical channel transistor) DRAM: CXMT, lacking EUV access, is pushing it aggressively, while Micron is skipping it in favor of continued 2D scaling, wafer-on-wafer bonding, and an eventual move to 3D DRAM. The divergence points to a potential inflection point in the industry, though there is broad agreement that 3D DRAM is the long-term destination and the real debate is over how to navigate the final stages of 2D scaling. As cell scaling runs out of room, competitive advantage is shifting toward back-end integration, fab expansion, and an increasingly important role for IP and trade policy.

What the Full Report Will Cover

  • How CXMT’s 4F² strategy differs from Micron’s bonding roadmap, and where Samsung and SK hynix sit between them.
  • The technical basics of 6F² vs. 4F² vs. wafer-on-wafer bonding, including scaling efficiency and sensing-margin limits.
  • Bonding timelines by vendor
  • How the 2D-to-3D transition could reset competition and shift policy from export controls toward IP and trade barriers.


Who Should Read This

  • Memory and semiconductor strategists tracking DRAM roadmaps and competitive positioning.
  • Equipment and materials suppliers exposed to etch, bonding, and EUV demand shifts.
  • Investors and analysts covering Samsung, SK hynix, Micron, CXMT.
  • Policy and supply-chain teams assessing how China’s memory self-sufficiency affects trade and sourcing.


Key Questions the Report Answers

  • Is CXMT’s claimed cell-area reduction from 4F² realistic, and can it reach mass production by the end of 2026?
  • Why are Micron, Samsung, and SK hynix prioritizing bonding over 4F², and does timing give any of them a decisive edge?
  • Is 4F² vs. bonding another “trench vs. stack” moment that separates winners from losers?
  • How will the move to 3D DRAM, which depends less on EUV, change competitive dynamics and geopolitical intervention?