Overview

This Foundry Monthly Intelligence Report provides timely, always-on market intelligence to keep you aligned with the latest developments in the foundry ecosystem. It includes ad hoc deep dives into emerging trends and market shifts, along with concise analyst takeaways that deliver real-time, decision-ready insights to support strategic planning and execution.

Table of Contents

The Fight for the Base Die: Why Memory Integration Is Now the Real Battleground 

  • TSMC and Samsung have stepped into the memory value chain, as HBM4 has doubled the channel count and therefore requires advanced-node base-die production.
  • NVHBM replaced JEDEC’s parallel bus with a private narrow interface to free up leading-edge compute area by reducing the area occupied by PHY and controller circuits.
  • NVLink Fusion extends beyond the interconnect and into the memory subsystem, giving it ownership of the fabric, rack, and memory interface. Trainium4 might be the first collaborator.
  • Qualcomm developed HBC (High Bandwidth Compute) rather than HBM and used wafer-to-wafer bonding with TSVs.
  • Semiconductor value is shifting from transistor density to packaging interfaces, with incremental value focused on advanced-node base dies, controllers, interface IP, etc.
  • With HBM continuing to lead AI training, near-memory architectures might first be adopted for inference and long-context decoding. We believe that nobody will win outright.

EUV Remains the Gatekeeper of Scaling: Divergent High-NA EUV Roadmaps Among Foundry Players 

  • The top three foundries have their own High-NA roadmaps: Intel Foundry adopted High-NA layers in its 18A process in 2026; Samsung is targeting memory processes from 2028, with logic processes following in 2029; while TSMC has deferred production until 2030 and beyond.
  • TSMC’s conservatism reminds us that tool leadership translates into profitability only when yield and defect-density performance also lead the industry.
  • ASML’s position as the sole supplier might strengthen further, as High-NA EUV costs twice as much as traditional EUV, and none of the leading foundry players can afford to be structurally short of High-NA capability at nodes where their competitors are already in production.

Imbalanced Supply/Demand Situation Caused Price Hikes in Wafer Manufacturing and Chip Packaging throughout 2026

  • Prices increased across foundry and packaging services, advanced and mature nodes, and Chinese and non-Chinese suppliers.
  • TSMC increased not only N2 and N3 wafer prices but also prices for 8-inch wafers for smaller clients, forcing them to source from other suppliers. Samsung adopted the same approach and even stopped accepting orders from new clients in the first half of 2026.
  • Samsung’s SF4 maintained strong price-hike momentum because of HBM4 base-die demand, while SF2 prices remained stable for customers other than Tesla.

Broadcom's XPU Boom Is Crowding Out TSMC's Advanced Packaging Capacity

  • Broadcom has become the second-largest CoWoS customer, with demand growing from 76k in 2025 to 238k in 2026 and 381k in 2027.
  • Google’s TPU v7/v8i keeps Broadcom anchored to the mature CoWoS-S platform, forcing TSMC to retain CoWoS-S resources and slowing the planned migration to CoWoS-L.
  • Despite aggressive expansion at AP7, AP9, and AP10, additions to CoW process and test equipment capacity still lag behind the combined demand from ASICs and GPUs.

  If you are interested in subscribing to the full report or would like to learn more, please contact us at [email protected].