The $Trillion Bottleneck: Inside Qualcomm's High Bandwidth Compute (HBC) Bet
- Qualcomm’s HBC is the most architecturally interesting response to the memory wall, and the reasoning looks incredibly sound
- Qualcomm’s HBC places a compute die beneath a 3D-stacked LPDDR array on a plain organic substrate, challenging the HBM-plus-interposer approach head-on.
- The architectural claim based on arithmetic intensity at the memory-to-compute boundary to do as much computation closer to the memory.
- HBC is different from custom-HBM and its all about minimizing the data movement out of the memory to accelerator.
- From Packaging perspective it’s a boon and a bane. No interposer, HBM allocation needed. Wafer-to-Wafer drives interconnect density, lower thermals but poses other packaging headaches. Who will be the anchor packaging and memory partner remains to be seen aka NVIDIA-TSMC-SK hynix trifecta.
- The commercial claim is still unproven. Gen 1 does not sample until mid-2027, Gen 2 until 2028, and nothing has been independently benchmarked yet. Competition can catch up. Software and tool chain will be the key.
The modern AI hardware race is on the ascent. We estimate more than 130 million accelerators (GPU + AI ASIC) for AI servers will cumulatively ship with advanced packaged on-compute memory in tow generating almost $2 Trillion in just compute revenues over the next five years. However, this opportunity gets even larger when we add NPU or Wafer-scale based acceleration from likes of Qualcomm, Rebellions, Positron AI, Cerebras and others targeting the massive AI Inferencing segment.
This AI tsunami comes with significant, complex design, IP, integration, raw materials and manufacturing challenges that the industry will have to out-innovate and solve.
One of the big bottlenecks we see is advanced packaging spanning compute, memory and interconnects. But these are converging. We believe the convergence will help overcome the physical limitations of traditional semiconductor scaling to power next-generation AI HPC systems:
- Eliminate ‘Memory Wall’
- Eliminate ‘Performance Wall’
- Eliminate ‘Copper Wall’
| The Wall | Memory Wall |
| The bottleneck | Bandwidth and capacity per watt — the memory subsystem, not the logic die, gates accelerator performance |
| Packaging answer | Qualcomm Wafer-to-Wafer Bonding stacking DRAM dies closer to compute |
| Why it converges | Near-Memory Compute becomes a thoughtful approach as most of the data processing doesn’t have to leave memory |
Source: Counterpoint Research
This series has spent most of its length on how the industry is rearranging silicon around a single constraint for example with Intel's EMIB family and its 3.5D variants, TSMC's CoWoS-S, CoWoS-L and CoWoS-R, Intel's ZAM and XBM set against conventional HBM4 and beyond stacking. Different as they are, every one of them answers the same question: how do you move more bytes per second between a large logic die and a large pool of DRAM, at a bump pitch and an IR drop you can manufacture?
Qualcomm's answer, disclosed at its June 2026 Investor Day and elaborated across an engineering blog series in July, is to decline the question. Instead of widening the channel between memory and compute, High Bandwidth Compute (HBC) moves a portion of the compute underneath the memory stack and leaves it there. In this series of research notes and our hypothesis on the advanced packaging trends, we will today deep dive into the evolving race to break down some of the walls. Memory Wall is the biggest challenge at this point.
We talked about Intel’s approach with EMIB, ZAM and XBM to take on TSMC’s CoWoS in previous analysis.
The $Trillion Bottleneck: Intel Bets EMIB, ZAM and XBM Against TSMC’s CoWoS
Decoding Qualcomm HBC vs HBM
A conventional accelerator sets HBM stacks and the XPU side by side on a silicon interposer. Every parameter byte the model touches is read out of the DRAM, driven laterally across tens of thousands of interposer traces, and consumed on the far side. The interposer exists because that lateral crossing needs an enormous number of very fine wires.
Read the full report: The $Trillion Bottleneck: Inside Qualcomm's High Bandwidth Compute Bet
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Author
Neil Shah
Neil is a sought-after frequently-quoted Industry Analyst with a wide spectrum of rich multifunctional experience. He is a knowledgeable, adept, and accomplished strategist. In the last 18 years he has offered expert strategic advice that has been highly regarded across different industries especially in telecom. Prior to Counterpoint, Neil worked at Strategy Analytics as a Senior Analyst (Telecom). Neil also had an opportunity to work with Philips Electronics in multiple roles. He is also an IEEE Certified Wireless Professional with a Master of Science (Telecommunications & Business) from the University of Maryland, College Park, USA.