The $Trillion Bottleneck: Intel Bets EMIB, ZAM and XBM Against TSMC’s CoWoS
- AI accelerator shipments will drive advanced packaging demand at scale: over 130 million GPUs/AI ASICs are expected to ship with advanced-packaged on-compute memory over the next five years, generating almost $2 Trillion in compute revenue.
- Packaging and not logic scaling is the new competitive battleground, as the industry works to break three converging physical limits of the Memory Wall, the Performance Wall, and the Copper Wall.
- HBM's reliance on TSMC's CoWoS silicon interposers carries steep costs with thick packages, yield risk, capacity constraints and high scrap costs, thus, creating an opening for credible alternatives.
- Intel is offering a theoretically attractive architectural solution for the memory interface on three fronts: EMIB (its proven, commercial packaging platform today), ZAM (a near-to-mid-term HBM4-class challenger developed with SoftBank's SAIMEMORY), and XBM (a longer-term BEOL thin-film-transistor and serial UCIe redesign).
- TSMC still leads on high-volume manufacturing, maturity and JEDEC-standard ecosystem lock-in, catching up on like-by-like innovation for CoWoS. So, Intel's ability to challenge CoWoS depends on timely execution, ecosystem buy-in (e.g., Google/MediaTek or tier-1 Memory partner), and resolving thermal and integration tradeoffs across EMIB, ZAM and XBM.
The modern AI hardware race is on the ascent. We estimate more than 130 million accelerators (GPU + AI ASIC) for AI servers will cumulatively ship with advanced packaged on-compute memory in tow generating almost $2 Trillion in just compute revenues over the next five years. This AI tsunami comes with significant, complex design, IP, integration, raw materials and manufacturing challenges that the industry will have to out-innovate and solve.
One of the big bottlenecks we see is advanced packaging spanning compute, memory and interconnects. But these are converging. We believe the convergence will help overcome the physical limitations of traditional semiconductor scaling to power next-generation AI HPC systems:
- Eliminate ‘Memory Wall’
- Eliminate ‘Performance Wall’
- Eliminate ‘Copper Wall’
| The Wall | Memory Wall | Performance Wall | Copper Wall |
| The bottleneck | Bandwidth and capacity per watt — the memory subsystem, not the logic die, gates accelerator performance | Reticle limits and 2D floorplans — you cannot buy more compute by growing the die | Electrical copper I/O — power and reach collapse as data rates climb |
| Packaging answer | HBM hybrid bonding; ZAM, XBM and other post-HBM interfaces | 3.5D stacking, chiplets, EMIB and full-reticle interposers | Co-packaged optics; glass and panel-level substrates |
| Why it converges | Memory must sit closer to compute | Compute must be disaggregated then re-joined | The link between them must stop being copper |
Source: Counterpoint Research
In this series of research notes and our hypothesis on the advanced packaging trends, we will today deep dive into the evolving race to break down some of the walls. Memory Wall is the biggest challenge at this point.
Read the full report: The $Trillion Bottleneck: Intel Bets EMIB, ZAM and XBM Against TSMC’s CoWoS
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Author
Neil Shah
Neil is a sought-after frequently-quoted Industry Analyst with a wide spectrum of rich multifunctional experience. He is a knowledgeable, adept, and accomplished strategist. In the last 18 years he has offered expert strategic advice that has been highly regarded across different industries especially in telecom. Prior to Counterpoint, Neil worked at Strategy Analytics as a Senior Analyst (Telecom). Neil also had an opportunity to work with Philips Electronics in multiple roles. He is also an IEEE Certified Wireless Professional with a Master of Science (Telecommunications & Business) from the University of Maryland, College Park, USA.